The development of electronic devices contributes to the speeding up of the operation of semiconductor integrated circuits (LSI) used in a CPU or GPU of a computer, a digital television, a smartphone, and the like. Particularly, image processing LSI or the like is being speeded up and highly integrated, and thus is desired to further reduce its size or respond to the increase in number of I/O terminals.
With the miniaturization and increase in number of the I/O terminals at the same time, the miniaturization or decrease of a terminal pitch is further progressed, which makes it difficult to mount a semiconductor integrated circuit on a package wiring substrate.
A ceramic substrate having excellent heat conductivity is hitherto used as the wiring substrate for the LSI package. The ceramic substrate has not only the excellent heat resistance and humidity resistance, but also small heat expansion coefficient and low warpage, and therefore is appropriate for metal bonding, such as soldering. However, the ceramic substrate is difficult to fire in a large size. It tends to cause cracks, and thus, the ceramic substrate is not appropriate for thinning.
A build-up wiring substrate is generally formed of a plurality of build-up layers including an interlayer insulating layer, a via hole, and a copper foil wiring layer stacked on both sides of a core substrate made of an organic material, such as an epoxy resin. Such build-up wiring substrate is used as a wiring substrate for the LSI package. For example, Patent Document 1 discloses a build-up substrate which is produced by forming a via hole (photovia process) using a photosensitive build-up resin insulating material, and then by forming wirings by copper plating (see with FIG. 13). Patent Document 2 discloses a build-up substrate which is produced by forming a via hole in a build-up insulating layer by laser process (in a photovia process), and then forming wirings by copper plating in the same way as the above document. Further, Patent Document 3 discloses a method (conformal process) which involves previously forming an opening in a copper foil by etching, and forming a fine via hole in a layer of interest by performing laser processing on the opening (see with FIG. 14).
In the latest CPU, the microfabrication is progressing up to 22 nm, while the number of I/O terminals is increasing and circuits are becoming larger. Applications of servers increasingly require the larger-sized semiconductor integrated circuit chip. The use of such a large-sized chip causes warpage of even the normal build-up substrate during a manufacturing process or due to a heat history during mounting of a LSI chip, which might peel off a soldered portion of a joint. Additionally, the miniaturization of a small-sized via hole process or a fine wiring pitch reduces the insulating reliability, which might decrease the withstand voltage or cause insulating failure. Recently, in order to meet the requirement for the further thinning, devices using a substrate consisting of only a build-up layer in place of the core substrate are being increasingly employed. For this reason, an insulating material with higher reliability that is applicable for the thinned devices is required.